LZ是北邮电子院研三的，现在在爱立信北京研发中心实习，因为准备找工作了，近期将离职。想内推一位北邮同学来接替我的工作。老板是北邮毕业的，所以你们懂得……
我的部门主要是做CDMA产品的FPGA、CPLD设计与验证，部门的氛围很好，人都很nice，能学到不少东西，如果你想在数字逻辑设计方面发展，来这错不了，不想做设计的也可以转验证。
发一个正式员工的JD吧
Job Description for FPGA Design Engineer
Software Developer
Description:
• FPGA functional design with VHDL.
• FPGA simulation and verification strategy planning and architecture design.
• Feature point extraction and test case planning and design and debugging.
• Documentation for related tasks, also be responsible for document review, code inspection and other tasks required by quality process.
• Familiar with ClearCase.
Qualifications:
• More than 3 years working experience on FPGA design and verification in Telecommunication product field. [color=#0000FF]（这条可忽略）[/color]
• Good Knowledge on FPGA design process, procedure, knowledge on verification methodology, OVM is a plus
• Be familiar with standard HW protocol and interfaces and IO standards, SRIO, PCI, PCI-e, Local bus, SERDES, I2C, SGMII, Flash/SDRAM.
• Good understanding of IO timing, system/FPGA clocking, system/FPGA reset structure and strategy.
• Good sense of co-working with team members under ClearCase like source control environments is a plus.
其他要求：北邮刚上研二的学生（其他学校的同学抱歉了），能保证每周三、四天的出勤率，半年以上的实习期。老板说女生优先考虑（team的男女比例很不协调）。专业能力见上，良好的数字逻辑设计、验证基础是需要的，其他的可以去了学习。
待遇：爱立信研究生都是20rmb/h。
如果觉得合适，可以把你的简历发给我：34827440@qq.com（内部邮箱就不留了，怕广告什么的），我将把简历转给我们的老板，谢谢。
我的部门主要是做CDMA产品的FPGA、CPLD设计与验证，部门的氛围很好，人都很nice，能学到不少东西，如果你想在数字逻辑设计方面发展，来这错不了，不想做设计的也可以转验证。
发一个正式员工的JD吧
Job Description for FPGA Design Engineer
Software Developer
Description:
• FPGA functional design with VHDL.
• FPGA simulation and verification strategy planning and architecture design.
• Feature point extraction and test case planning and design and debugging.
• Documentation for related tasks, also be responsible for document review, code inspection and other tasks required by quality process.
• Familiar with ClearCase.
Qualifications:
• More than 3 years working experience on FPGA design and verification in Telecommunication product field. [color=#0000FF]（这条可忽略）[/color]
• Good Knowledge on FPGA design process, procedure, knowledge on verification methodology, OVM is a plus
• Be familiar with standard HW protocol and interfaces and IO standards, SRIO, PCI, PCI-e, Local bus, SERDES, I2C, SGMII, Flash/SDRAM.
• Good understanding of IO timing, system/FPGA clocking, system/FPGA reset structure and strategy.
• Good sense of co-working with team members under ClearCase like source control environments is a plus.
其他要求：北邮刚上研二的学生（其他学校的同学抱歉了），能保证每周三、四天的出勤率，半年以上的实习期。老板说女生优先考虑（team的男女比例很不协调）。专业能力见上，良好的数字逻辑设计、验证基础是需要的，其他的可以去了学习。
待遇：爱立信研究生都是20rmb/h。
如果觉得合适，可以把你的简历发给我：34827440@qq.com（内部邮箱就不留了，怕广告什么的），我将把简历转给我们的老板，谢谢。
